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AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 1 AT83C5103 / at87c5103 c51 lpc 8-bit microcontroller atmel p/n : at8xc5103xxx-ibral ppap submission date: march 2003 supplier: atmel-nantes sa address: la chantrerie bp 70602 44306 nantes cedex 3 france tel : 33(0) 2 40 18 18 18 fax : 33(0) 2 40 18 19 20
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 2 table of contents table of contents.............................................................................................................. ...............................................2 revision history............................................................................................................... ..................................................4 ppap checklist ................................................................................................................. ....................................................5 1 design records ................................................................................................................. ..........................................6 1.1 p roduct s pecification ............................................................................................................................... ............6 1.2 p ackage o utline ............................................................................................................................... .........................6 2 engineering change documents ................................................................................................... ..................6 2.1 cdc c ertificate of d esign , c onstruction and q ualification ...................................................................6 2.1.1 general product information .................................................................................................... ...............................6 2.1.2 process technology information................................................................................................. .............................7 2.2 p roduct d esign ............................................................................................................................... .........................8 2.2.1 product design in formation..................................................................................................... ................................8 2.2.2 package technology information................................................................................................. ............................8 2.2.3 packing delivery information ................................................................................................... ...............................9 2.2.4 final test information......................................................................................................... .....................................9 2.2.5 device cross section........................................................................................................... ...................................10 2.3 q ualification and c hange p rocedure .............................................................................................................11 2.3.1 qualification methodology ...................................................................................................... ...............................11 2.3.2 change procedure............................................................................................................... ...................................12 2.3.3 qualification test methods..................................................................................................... .................................13 3 engineering approval ........................................................................................................... ..............................14 4 design fmea .................................................................................................................... .............................................14 5 process flow diagrams .......................................................................................................... ............................14 5.1 f rontend ............................................................................................................................... ...................................14 5.2 a ssembly ............................................................................................................................... ...................................15 5.3 t est and p acking ............................................................................................................................... ......................15 6 process fmea ................................................................................................................... ...........................................15 7 dimentional results ............................................................................................................ ................................16 8 performance te st resu lts ....................................................................................................... ........................16 8.1 q ualification r esults ............................................................................................................................... ..........16 8.1.1 wafer process qualification .................................................................................................... ..............................16 8.1.2 package qualification .......................................................................................................... ..................................16 8.1.2.1 product qualification.......................................................................................................... .............................................17 8.1.2.2 device relia bility ............................................................................................................. ...............................................17 8.1.2.3 package reliability ............................................................................................................ ..............................................17 8.1.2.4 electrical distribution in operating life-test ................................................................................. ................................18 8.1.2.5 failure mechanisms and corrective actions ...................................................................................... .............................18 8.1.2.6 esd results (hbm) - mil-std 883e method 3015.7 ................................................................................. ..................18
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 3 8.1.2.7 latchup results................................................................................................................ ................................................18 8.2 p roduct c haracterization ............................................................................................................................... .18 8.2.1 characterization environment................................................................................................... .............................18 8.2.2 corner lot?s splits ............................................................................................................ .......................................18 8.2.3 results / para meter capability ................................................................................................. ..............................19 8.2.3.1 input voltages................................................................................................................. .................................................19 8.2.3.2 output voltages ................................................................................................................ ...............................................20 8.2.3.3 input currents ................................................................................................................. ..................................................21 8.2.3.4 pull-down resistor on reset pin................................................................................................ .....................................22 8.2.3.5 consump tions ................................................................................................................... ...............................................22 9 initial proc ess study.......................................................................................................... ..................................23 9.1 scmos3 process (z92g) ............................................................................................................................... ........23 9.2 scmos3nv process (z94x) ............................................................................................................................... ...24 10 measurement system analysis study .............................................................................................. ......25 11 qualified laboratory documentation ............................................................................................. ..25 12 control plan................................................................................................................... ......................................25 13 part submissi on warrant........................................................................................................ ......................26 14 appearance appr oval report..................................................................................................... ................27 15 bulk material requirements..................................................................................................... ................27 16 sample product ion parts ........................................................................................................ ......................27 17 master sample .................................................................................................................. ....................................27 18 checking aids .................................................................................................................. ......................................27 19 customer-specific requirements ................................................................................................. ...........27
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 4 revision history rev issue modification notice applicable from 0 january 2003 initial version 1 march 2003 update after product characterization completion (3v and 5v ranges)
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 5 ppap checklist requirements included table of contents yes ppap checklist yes 1. design records yes 2. engineering change documents yes 3. engineering approval yes 4. design fmea project risk analysis 5. process flow diagrams yes 6. process fmea yes 7. dimensional results not applicable 8. records of material / performance test results 8.1 material test records 8.2 performance test records not applicable to ic yes 9. initial process study yes 10. measurement system analysis study yes 11. qualified laboratory documentation yes 12. control plan yes 13. part submission warrant (psw) yes 14. appearance approval report not applicable to ic 15. bulk material requirements checklist not applicable to ic 16. sample production parts separate order 17. master sample not attached 18. checking aids not applicable 19. customer specific requirements not defined
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 6 1 design records 1.1 product specification please see atmel?s data sheet AT83C5103 / at87c5103 low-pin-count 8-bit microcontroller http://www.atmel.com/ 1.2 package outline see attached file : ssop16_outline.pdf 2 engineering change documents 2.1 cdc certificate of design, construction and qualification 2.1.1 general product information product name: at87c5103: 16k eprom AT83C5103: 16k rom function: 8 bits microcontroller, 16kbytes memory wafer process: cmos 0.5um package type : ssop 16 locations: process development, atmel nantes , france product development atmel nantes , france wafer plant atmel nantes , france qc responsibility atmel nantes, france probe test atmel nantes , france assembly amkor philippines final test tsti philippines lot release atmel nantes, france shipment control global logistic center, philippines quality assurance atmel nantes, france reliability testing atmel nantes, france failure analysis atmel nantes, france
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 7 2.1.2 process technology information process type (name): z94 (scmos3 non volatile - eprom) z92 (scmos3 - rom) base material: epi (z94) bulk (z92) wafer thickness (final) 475m wafer diameter 150 mm number of masks z94: 22 z92: 14 gate oxide (logic transistors) material silicon dioxide thickness 110 a gate oxide (eprom cell) material silicon dioxide thickness 110 a polysilicon number of layers z94:2 z92:1 thickness poly 1 2000a thickness poly 2 3000a metal number of layers 3 material: alcu layer 1 thickness 5150a layer 2 thickness 5150a layer 3 thickness 7650a passivation material z94: sio2 / oxynitride z92: sio2 / nitride thickness z94: 3000a / 15000a z92: 2600a / 6400a
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 8 2.2 product design 2.2.1 product design information die size 3500m * 3090m (10.82mm2) pad size opening 80m * 80m logic effective channel length 0.5 m gate poly width (min.) 0.50 m gate poly spacing (min.) 0.60 m metal 1 width 0.60 m metal 1 spacing 0.70 m metal 2 width 0.80 m metal 2 spacing 0.70 m metal 3 width 0.80 m metal 3 spacing 0.70 m contact size 0.60m via 1 size 0.60m via 2 size 0.60m 2.2.2 package technology information package weight 0.14 g chip separation method sawing lead frame material cu thickness 6 mils lead plating electroplated sn/pb 85/15 die attach material silver epoxy type ablestick 84-1 lmisr4 wire bonding material au diameter 1.0 mil method thermosonic molding material mp8000an flammability rating ul94v-0 marking method top : printed ink back : laser
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 9 2.2.3 packing delivery information dry packing no tube packed primary tube material antistatic pvc number per unit 77 secondary box material cardboard number per unit 385 labelling (minimum) device type, quantity, date code, production code bar coding code 39 to eia-556-a reel packed primary reel material carrier tape conductive black polystyrene cover tape antistatic film number per unit 2000 secondary box number per unit 1 labelling (minimum) device type, quantity, date code, production code 2.2.4 final test information probe equipment maverick gt or pt probe temperature 125 o c test equipment maverick gt or pt test temperature - 40 o c + 125 o c + 25 o c
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 10 2.2.5 device cross section
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 11 2.3 qualification and change procedure 2.3.1 qualification methodology all product qualifications are split into three distinct steps as shown below. before a product is released for use, successful qualification testing are required at wafer, device and package level. - wafer level reliability consists in testing individua lly basic process modules regarding their well known potential limitations (electromigration, hot carriers injection, oxide breakdown, nvm data retention). each test is performed using wafer process specific structures. - device reliability is covering either dice design and processing aspects. the tests are performed on device under qualification, but generic data may also be considered for reliability calculation. - for each package type proposed in the datasheet, it is verified that qualification data are available. if not qualification tests are carried out for the new package types. in addition, one package type is selected to verify packaging reliability of the device under qualification. product qualification wafer level reliability device reliability packaging reliability (design / process)
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 12 2.3.2 change procedure all changes are controlled by ecn (engineering change notice). all major changes are notified to the customers using products that are affected by the change. a major change is defined as a change which affects the electrical and/or mechanical specification as defined in the datasheet or wh ich affects the following parameters as defined hereafter: 1 general major changes 1-1 manufacturing line 1-2 sequence of fabrication process cycle 1-3 material type 1-4 electrical parameter 1-5 external physical dimension 1-6 die size 2 changes specific to wafer fabrication area 2-1 doping method 2-2 gate oxide formation method 2-3 equipment change 2-4 layer thickness 2-5 module dimensions 3 changes specific to assembly process area 3-1 sawing method 3-2 die attach 3-3 wire interconnect tools 3-4 molding process 3-5 tinning method 4 changes specific to test area 4-1 specification limit 4-2 test coverage reduction 4-2 product identification 4-3 final conditioning
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 13 2.3.3 qualificati on test methods general requirements for plastic packaged cmos ics. standard test description acceptance mil-std 883 method 1005 electrical life test (early failure rate) 48 hours 140c 0/300 - 48h mil-std 883 method 1005 electrical life test (latent failure rate) 1000 hours 140c dynamic or static 0/100 - 500h mil-std 883 method 3015.7 electrostatic discharge hbm +/-2000v 1.5kohm/100pf/3 pulses 0/3 per level jedec 78 latch up 50mw power injection, 50% overvoltage @125c 0/5 per stress aec q100 method 005 nvm endurance program erase cycles 25c 0/50 - 100kc aec q100 method 005 nvm data retention high temperature storage 165c 0/50 - 500h mil-std 883 method 1010 temperature cycling 1000 cycles -65c/150c air/air 0/50 - 500c atmel paqa0184 hast after preconditioning 144 hours 130c/85%rh 0/50 - 72h eia jesd22-a101 85/85 humidity test 1000 hours 85c/85%rh 0/50 - 500h eia jesd22-a110 hast 336 hours 130c/85%rh/5.5v 0/50 - 168h eia jedec 20-std preconditioning soldering stress 220c/235c/3 times 0/11 per class mil-std 883 method 2003 solderability 0/3 mil-std 883 method 2015 marking permanency 0/5
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 14 3 engineering approval at8xc5103 is qualified since january 2003 released to production is planned on february 2003 release to production loop approval is the following : head of technical center technical project leader project manager product engineering operation backend operation frontend quality management marketing business planning test development 4 design fmea for new products, a project risk analysis is performed during feasibility phase under the project leader responsibility, using expertise in many areas including design. this project risk analysis and related action plan to reduce the risks are reviewed at each milestone of the project. the project risk analysis report is an atmel internal document . 5 process flow diagrams 5.1 frontend 1. incoming inspection of silicon wafers. 2. pbl (z94) or locos (z92) isolation. 3. non volatile well implants (z94). 4. mos n-well implants (z94 & z92) and n well diffusion. (z92) 5. eprom floating gate oxidation and poly deposition (z94). 6. eprom ono stack oxidation (z94). 7. hvmos gate oxidation (z94) 8. mos p-well implants (z94 & z92). 9. depleted mos well implants (z94). 10. mos definition (z94). 11. mos gate oxidation (z94 & z92). 12. polysilicon deposition and mos gate definition(z94 & z92). 13. eprom control gate definition (z94) and eprom implants (z94).
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 15 14. mos / hvmos implants with spacer definition. (z94 & z92) 15. silicide hard mask definition.(z94 & z92) 16. salicide module. (z94 & z92) 17. ild deposition and sog planarization (z94 & z92) 18. contact etching and plug1 filling. (z94 & z92) 19. metal 1 deposition and etching (z94 & z92) 20. imd1 and reb planarization (z94 & z92) 21. via1 etching and plug2 filling (z94 & z92) 22. metal 2 deposition and etching (z94 & z92) 23. imd2 and reb planarization (z94 & z92) 24. via2 etching and plug3 filling (z94 & z92) 25. metal 3 deposition and etching (z94 & z92) 26. passivation deposition and etching (z94 & z92) 27. uv erasing (z94) 28. test site (z94 & z92) 29. wafer sort1 (z94 & z92) 30. bake (z94) 31. wafer sort2 (z94) 5.2 assembly referenced process flow chart : amkor philippines p470-0501-0204 1. wafer mount 2. wafer saw 3. first optical 4. die bonding 5. wire bonding 6. molding 7. solder plating 8. top marking 9. trim and form 10. final visual inspection 5.3 test and packing 1. room temperature initial test 2. burn-in 3. room temperature test 4. hot test 5. cold test 6. final quality checks 7. packing 6 process fmea process fmea for 0.5um z92 and z94 are implemented and are only shown upon request during customer audits.
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 16 7 dimentional results only necessary for new packages and/or new assembly locations/lines not necessary for this ppap, because parts are produced in standard ssop16 package package dimensions were checked during package qualification (see chapter 8.1.2 for more details) 8 performance test results 8.1 qualification results 8.1.1 wafer process qualification atmel 0.5m scmos3 wafer process is qualified since 1997, september atmel 0.5m scmos3nv wafer process is qualified since 2000, february 8.1.2 package qualification performed on product g1001 at amkor philippines : qtp 0329 (11/10/1996) the following table summarizes the ssop16 package qualification results test description step result comment humidity 85c/85rh 1000h 0/45 thermal cycles ? 65c/100c 1000c 0/45 lead finish adhesion 0/3 construction analysis 0/5 ac96009 marking permanency 0/5 ir reflow mounting 168h 0/45 with preconditionning physical dimentions 0/5 ir reflow mounting 168h 0/45 without preconditionning conclusions : no failure was observed during the reliability tests. the qualification of ssop16l at amkor philippines is pronounced.
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 17 8.1.2.1 product qualification 8.1.2.2 device reliability the test results are summarized in the table below: lot device type test description step result comment z42859b AT83C5103 efr dynamic life test 12h 0/800 lfr life test 500h 1000h 0/77 0/77 z40807c tss463 efr dynamic life test 12h 1/776 overstress lfr life test 500h 1000h 0/77 0/77 z27921a ts83c51rx2 efr dynamic life test 12h 0/297 lfr life test 500h 1000h 0/100 0/100 z27300a ts83c51rc2 esd hbm 4000v 0/3 class 3 of mil std 883 method 3015 latch-up power injection over-voltage 50mw 10v 0/5 0/5 latch-up free (up to 120mw) 8.1.2.3 package reliability in this section are presented the packaging qualification measurements done on AT83C5103 in ssop16 . lots device type test description step result comment z42859b AT83C5103 85/85 humidity 500h 1000h 0/77 0/77 after preconditioning level1 thermal cycles 500c 1000c 0/77 0/5 0/5 0/72 after preconditioning level1 ball shear cpk:1.22 (30 pads) wire pull cpk:1.39 (30 wires) hast after soldering stress 96h 0/77 high temperature storage 165c 500h 1000h 0/77 0/77 moisture sensitivity jesd20 ? level1 csam elect 0/11 0/231
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 18 8.1.2.4 electrical distribution in operating life-test not available 8.1.2.5 failure mechanisms and corrective actions not applicable 8.1.2.6 esd results (hbm) - mil-std 883e method 3015.7 product 87c5103 is classified in class 1 of the mil-std product 83c5103 is classified in class 3 of the mil-std 8.1.2.7 latchup results power injection 50mw 0/5 latch-up free (up to 120mw) over-voltage 10v 0/5 8.2 product characterization 8.2.1 characterization environment tester: maverick 2 / ntomv23 corner lot: z42859 process: z92g - bulk rom code: 3zaa assy package: 3z (pdil24.300) 8.2.2 corner lot?s splits in order to characterize the product with realistic excursion of the process, corner run splits have been manufactured using : variation onsleffp and leffn variations on vtp and vtn
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 19 8.2.3 results / parameter capability 8.2.3.1 input voltages symbol parameter specification vcc temp average cpk conditions -40c 1.22v 4.2 1.89v max 2 .7v 130c 1.09v 5.7 -40c 1.42v 4.5 2.31v max 3 .3v 130c 1.29v 5.6 -40c 1.5v 5.0 2.52v max 3.6v 130c 1.39 5.7 -40c 1.77v 6.8 3.15v max 4.5v 130c 1.68v 6.2 -40c 2.04v 7.2 vih input high level exept rst & xtal1 3.85v max 5.5v 130c 2.03v 7.1 -40c 0.99v 6.1 1.89v max 2.7v 130c 0.86v 4.7 -40c 1.13v 8.0 2.31v max 3.3v 130c 0.96v 8.4 -40c 1.2v 9.5 2.52v max 3.6v 130c 1.02v 11 .1 -40c 1.41v 11.4 3.15v max 4.5v 130c 1.22v 12.8 -40c 1.64v 13.5 vih1 input high level rst 3.85v max 5.5v 130c 1.44v 19.5 -40c 1.41v 8.0 1.89v max 2.7v 130c 1.45v 6.5 -40c 1.75v 7.0 2.31v max 3.3v 130c 1.79v 6.8 -40c 1.93v 6.8 2.52v max 3.6v 130c 1.97v 6.7 -40c 2.45v 6.4 3.15v max 4.5v 130c 2.5v 6.5 -40c 3.06v 6.2 vih1 input high level xtal1 3.85v max 5.5v 130c 3.1v 6.0 -40c 1.19v 3.2 0.44v min 2.7v 130c 1.06v 3.7 1.39v 3.0 0.56v min 3.3v -40c 130c 1.25v 3.1 1.48v 3.1 0.62v min 3.6v -40c 130c 1.35v 2.9 -40c 1.75v 2.9 0.8v min 4.5v 130c 1.62v 2.3 -40c 2.03v 2.1 vil input low level 1.0v min 5.5v 130c 1.92v 1.8
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 20 8.2.3.2 output voltages symbol parameter specification vcc temp average cpk conditions -40c 2.7v 163 2.2v min 2.7v 130c 2.7v 112 -40c 4.5v 138 4.0v min 4.5v 130c 4.5v 106 ioh = 0.1 ma -40c 2.35v 9.3 1.7v min 2.7v 130c 2.06v 2.5 -40c 4.27v 29 voh_pp output high level in push-pull mode ports 1 & 4 3.5v min 4.5v 130c 4.13v 15 ioh = 1ma -40c 4.41v 14.1 4.2v min 130c 4.35v 9.9 ioh = 10 a -40c 4.25v 15 3.8v min 130c 4.08v 7.3 ioh = 30 a -40c 4.0v 15.6 3.0v min 4.5v 130c 3.6v 5.9 ioh = 60 a -40c 2.57v 9.2 voh output high level in pseudo bidirectional mode ports 1 & 4 2.4v min 2.7v 130c 2.48v 3 ioh = 10 a -40c 0.05v 11.4 0.3v max 130c 0.08v 5.8 ioh = 0.1ma -40c 0.35v 2.2 0.45v max 130c 0.35v 1.9 ioh = 1.6ma -40c 0.72v 3.3 1.0v max 4.5v 130c 0.70v 3.8 ioh = 3.5ma -40c 0.05v 11.4 0.3v max 130c 0.08v 5.7 ioh = 0.1ma -40c 0.37v 13.5 vol output low level ports 1 & 4 1.0v max 2.7v 130c 0.39v 10.8 ioh = 1.6ma
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 21 8.2.3.3 input currents symbol parameter specification vcc temp average cpk conditions -40c -7 a 26.2 3.3v 130c -4 a 56.4 -40c -8.3 a 22.2 3.6v 130c -4.9 a 48 -40c -19.7 a 8.8 iil input low current in pseudo bidirectional mode -50 a 5.5v 130c -11.8 a 21.6 vin = 0.45v -40c -94.1 a 32.8 3.3v 130c -56.1 a 67.9 -40c -119.4 a 25.2 3.6v 130c -71.6 a 52.6 -40c -301.5 a 7.6 itl input transition current in pseudo bidirectional mode -650 a 5.5v 130c -189.8 a 17.8 vin = 2v -40c 0.7na 188.5 3.3v 130c 2.7na 120.9 -40c 1.6na 184.7 3.6v 130c 3.5na 118.6 -40c 1.1na 186.3 5.5v 130c 4.1na 123 vin = 0v -40c 56na 107.5 3.3v 130c 78.4na 52.6 -40c 61.6na 106.6 3.6v 130c 68.6na 48.2 -40c 92na 75.4 ili_z input leakage current in input mode 10 a 5.5v 130c 48.2na 27.5 vin = vcc -40c 0.1na 181.9 3.3v 130c 3na 121.7 -40c 1.1na 180.8 3.6v 130c 3na 119.4 -40c 0.8na 182.7 5.5v 130c 2.9na 125.2 vin = 0v -40c 55.8na 106.9 3.3v 130c 81na 50.3 -40c 63na 101 3.6v 130c 88.2na 47.5 -40c 92.2na 71.5 ili_od input leakage current in open drain mode 10 a 5.5v 130c 150.6na 27.4 vin = vcc
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 22 8.2.3.4 pull-down resistor on reset pin symbol parameter specification vcc temp average cpk conditions -40c 39.4k 4.8 2.7v 130c 67.7k 7.1 -40c 39.7k 4.8 3.3v 130c 68.1k 7 -40c 39.8k 5 3.6v 130c 68.3k 6.9 -40c 40.2k 5.1 4.5v 130c 68.9k 6.7 -40c 40.7k 5.2 rpdrst pull-down reset resistor min = 30kohms max = 150kohms (rom version only) 5.5v 130c 69.5k 6.5 8.2.3.5 consumptions symbol parameter specification vcc temp average cpk conditions 3.3v 8 a 2.7 50 a max 3.6v 9 a 1.8 ipd power-down current 100 a max 5.5v 130c 16 a 2.2 see datasheet -40c 7.9ma 7.5 3.3v 130c 6.8ma 6.9 -40c 8.9ma 6.3 14.2ma max 3.6v 130c 7.7ma 5.7 -40c 15.2ma 5.8 iccop operating consumption 21.5ma max 5.5v 130c 13.9ma 5.1 16.7mhz cpu running -40c 5.5ma 5.9 3.3v 130c 4.8ma 7.7 -40c 6.2ma 4.6 10.8ma max 3.6v 130c 5.4ma 6.2 -40c 11.4ma 4.8 iccidl idle mode consumption 18.2ma max 5.5v 130c 9.9ma 6.0 16.7mhz cpu inactive
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 23 9 initial process study 9.1 scmos3 process (z92g) parameters controlled during electrical test : nmos/pmos :junction breakdown voltage, threshold voltage, electrical width & length, thin oxide breakdown voltage, sub-threshold current. sheet resistance : n+, p+, well, polyn, polyp, unsalicided poly metal continuity / isolation : metal1, metal2, metal3 contacts/ vias1 & vias2 resistance contacts breakdown voltage salicide isolation cpk history (last update 23/01/2003) z92g cpk distribution 0% 20% 40% 60% 80% 100% 120% mois rpartition (%) cpk<1.33 (%) cpk>=1.33 & <1.66 (%) cpk>=1.66 (%) linaire (cpk<1.33 (%)) linaire (cpk>=1.66 (%)) cpk<1.33 (%) 5% 3% 5% 8% 5% 5% 8% 0% 8% 14% 0% 3% 3% cpk>=1.33 & <1.66 (%) 5% 5% 3% 5% 19% 5% 11% 3% 5% 0% 3% 5% 3% cpk>=1.66 (%) 89% 92% 92% 86% 76% 89% 81% 97% 86% 86% 97% 92% 95% 02/01 02/02 02/03 02/04 02/ 05 02/06 02/07 02/08 02/09 02/10 02/11 02/12 03/01
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 24 9.2 scmos3nv process (z94x) parameters controlled during electrical test : same as z92g with eprom junction breakdown voltage, programmed threshold voltage, ono breakdown voltage high voltage mos : oxide breakdown voltage, high voltage threshold voltage, high voltage junction breakdown depleted mos : threshold voltage. cpk history (last update 23/01/2003) z94x cpk distribution 0% 20% 40% 60% 80% 100% 120% mois distribution (%) cpk<1.33 (%) cpk>=1.33 & <1.66 (%) cpk>=1.66 (%) linaire (cpk<1.33 (%)) linaire (cpk>=1.66 (%)) cpk<1.33 (%) 0% 22% 7% 9% 4% 7% 4% 4% 16% 4% 13% 4% 4% cpk>=1.33 & <1.66 (%) 5% 4% 2% 2% 2% 2% 7% 4% 0% 4% 9% 0% 0% cpk>=1.66 (%) 95% 73% 91% 89% 93% 91% 89% 91% 84% 91% 78% 96% 96% 02/01 02/02 02/03 02/04 02/05 02/06 02/07 02/08 02/09 02/10 02/11 02/12 03/01
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 25 10 measurement system analysis study repeatability and reproductability tests are performed on all the manufacturing equipments. critical parameters are followed by cpk but equipment performance is followed by grr and maintenance follow-up. 11 qualified laboratory documentation internal lab ? compliant qs-9000 3 rd edition scope application lab check the functionality of products to customer applications calibration lab standard gage calibration characterization lab product and process characterization before completing industrialization chemical lab incoming inspection on chemical products and process monitoring on di water , gases environmental lab reliability tests technology analysis lab failure analysis and yield enhancement 12 control plan see attached file : control plan for z92g process
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 26 13 part submission warrant
AT83C5103 - at87c5103 ppap rev. 1 : initial submission ? 2003 march 27 14 appearance a pproval report not applicable for ic 15 bulk material requirements not applicable for ic 16 sample production parts not attached, delivered previously 17 master sample not attached. 18 checking aids not applicable 19 customer-speci fic requirements not specified.

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